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Quad, 12-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC AD5726
FEATURES
+5 V to 15 V operation Unipolar or bipolar operation 1 LSB maximum INL error, 1 LSB maximum DNL error Guaranteed monotonic over temperature Double-buffered inputs Simultaneous updating via LDAC Asynchronous CLR to zero scale/midscale Operating temperature range: -40C to +125C iCMOS(R) process technology1
Bipolar outputs are configured by connecting both VREFP and VREFN to nonzero voltages. This method of setting output voltage ranges has advantages over the bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. The AD5726 uses a serial interface that operates at clock rates up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows simultaneous updating of all DACs. The asynchronous CLR function clears all DAC registers to a user-selectable, zero-scale or midscale output. The AD5726 is available in 16-lead SSOP and 16-lead SOIC packages. It can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 V to 15 V, and references ranging from +2.5 V to 10 V. Power dissipation is less than 240 mW with 15 V supplies and only 30 mW with a +5 V supply. Operation is specified over the temperature range of -40C to +125C. Table 1. Related Devices
Part No. AD5725 AD5724R/AD5734R/ AD5754R AD5722R/AD5732R/ AD5752R Description Quad, 12-bit, parallel input, unipolar/bipolar, voltage output DAC. Complete, quad, 12-/14-/16-bit, serial input, unipolar/bipolar voltage output DAC with internal reference. Complete, dual, 12-/14-/16-bit, serial input, unipolar/bipolar voltage output DAC with internal reference.
APPLICATIONS
Industrial automation Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers
GENERAL DESCRIPTION
The AD5726 is a quad, 12-bit, serial input, voltage output digital-to analog converter that offers guaranteed monotonicity and integral nonlinearity (INL) of 1 LSB maximum. Output voltage swing is set by two reference inputs, VREFP and VREFN. The DAC offers a unipolar positive output range when the VREFN input is set to 0 V and the VREFP input is set to a positive voltage. A similar configuration with VREFP at 0 V and VREFN at a negative voltage provides a unipolar negative output range.
FUNCTIONAL BLOCK DIAGRAM
AVSS AVDD VREFP
12 SDIN SCLK CS I/O REGISTER AND CONTROL LOGIC
INPUT 12 REG A INPUT 12 REG B INPUT 12 REG C INPUT 12 REG D
DAC 12 REG A DAC 12 REG B DAC 12 REG C DAC 12 REG D
DAC A
VOUTA
DAC B
VOUTB
DAC C
VOUTC
DAC D
AD5726
GND
VOUTD
06469-001
CLR CLRSEL LDAC
VREFN
Figure 1.
1
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD5726 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Performance Characteristics ................................................ 5 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 DAC Architecture....................................................................... 13 Output Amplifiers ...................................................................... 13 Reference Inputs ......................................................................... 13 Serial Interface ............................................................................ 14 Applications..................................................................................... 15 Power-Up Sequence ................................................................... 15 Reference Configuration ........................................................... 15 Power Supply Bypassing and Grounding................................ 16 Galvanically Isolated Interface ................................................. 16 Microprocessor Interfacing....................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
4/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5726 SPECIFICATIONS
AVDD = +5 V 5%, AVSS = 0 V/-5 V 5%, VREFP = +2.5 V, VREFN = 0 V/-2.5 V, RLOAD = 2 k. All specifications TMIN to TMAX, unless otherwise noted. 1 Table 2.
Parameter ACCURACY Resolution Relative Accuracy (INL) Differential Nonlinearity (DNL) Linearity Matching Zero-Scale Error Full-Scale Error Zero-Scale Error Full-Scale Error Zero-Scale TC 3 Full-Scale TC3 REFERENCE INPUT VREFP Reference Input Range 4 Input Current VREFN Reference Input Range4 Value 12 1 1 1 1 6 6 12 12 10 10 Unit Bits LSB max LSB max LSB max LSB typ LSB max LSB max LSB max LSB max ppm FSR/C typ ppm FSR/C typ Test Conditions/Comments
Y grade, AVSS = -5 V, outputs unloaded Y grade, AVSS = 0 V 2 Guaranteed monotonic AVSS = -5 V AVSS = -5 V AVSS = 0 V2 AVSS = 0 V2 AVSS = -5 V AVSS = -5 V
VREFN + 2.5 AVDD - 2.5 0.75 AVSS 0V VREFP - 2.5 -1.0 160 1.25 2.4 0.8 10 5 0.002 1.5 1.5 30
V min V max mA max V min V min V max mA max kHz typ mA max V min V max A max pF typ %/% max mA/channel max mA/channel max mW max
Typically 0.25 mA
AVSS = 0 V Typically -0.6 mA, AVSS = -5 V -3 dB, VREFP = 0 V to 10 V p-p AVSS = -5 V
Input Current Large Signal Bandwidth3 OUTPUT CHARACTERISTICS3 Output Current DIGITAL INPUTS VIH, Input High Voltage VIL, Input Low Voltage Input Current3 Input Capacitance3 POWER SUPPLY CHARACTERISTICS Power Supply Sensitivity3 AIDD AISS Power Dissipation
1 2
Typically 0.0004 Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V Outputs unloaded, typically 15 mW, AVSS = 0 V
All supplies can be varied 5% and operation is guaranteed. Device is tested with AVDD = 4.75 V. For single-supply operation (VREFN = 0 V, AVSS = 0 V), due to internal offset errors, INL and DNL are measured beginning at code 0x005. 3 Guaranteed by design and characterization, not production tested. 4 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
Rev. 0 | Page 3 of 20
AD5726
AVDD = +15 V 5%, AVSS = -15 V 5%, VREFP = +10 V, VREFN = -10 V, RLOAD = 2 k. All specifications TMIN to TMAX, unless otherwise noted. 1 Table 3.
Parameter ACCURACY Resolution Relative Accuracy (INL) Differential Nonlinearity (DNL) Linearity Matching Zero-Scale Error Full-Scale Error Zero-Scale TC 2 Full-Scale TC2 REFERENCE INPUT VREFP Reference Input Range 3 Input Current VREFN Reference Input Range3 Input Current2 Large Signal Bandwidth2 OUTPUT CHARACTERISTICS2 Output Current DIGITAL INPUTS VIH, Input High Voltage VIL, Input Low Voltage Input Current2 Input Capacitance2 POWER SUPPLY CHARACTERISTICS Power Supply Sensitivity2 AIDD AISS Power Dissipation
1 2
Value 12 0.5 1 1 3 3 4 4
Unit Bits LSB max LSB max LSB max LSB max LSB max ppm FSR/C typ ppm FSR/C typ
Test Conditions/Comments
Y grade Guaranteed monotonic
VREFN + 2.5 AVDD - 2.5 2 -10 V VREFP - 2.5 -3.5 450 5 2.4 0.8 10 5 0.002 2 2 240
V min V max mA max V min V max mA min kHz typ mA max V min V max A max pF typ %/% max mA/channel max mA/channel max mW max
Code 0x000, Code 0x555, typically 1 mA
Code 0x000, Code 0x555, typically -2 mA -3 dB, VREFP = 0 V to 2.5 V p-p
Typically 0.0004 Outputs unloaded, typically 1.25 mA, VIL = DGND, VIH = 5 V Outputs unloaded, typically 1.25 mA, VIL = DGND, VIH = 5 V
All supplies can be varied 5% and operation is guaranteed. Guaranteed by design and characterization, not production tested. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
Rev. 0 | Page 4 of 20
AD5726
AC PERFORMANCE CHARACTERISTICS
AVDD = +5 V 5%/+15 V 5%, AVSS = -5 V 5%/0 V/-15 V 5%, GND = 0 V, VREFP = +2.5 V/+10 V, VREFN = -2.5 V/0 V/-10 V, RLOAD = 2 k. All specifications TMIN to TMAX, unless otherwise noted. 1 Table 4.
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time (tS) Slew Rate Analog Crosstalk Digital Feedthrough Large Signal Bandwidth Glitch Impulse
1
A Grade 13 9 2.3 2 100 0.25 90 30
B Grade 13 9 2.3 2 100 0.25 90 30
Unit s typ s typ V/s typ V/s typ dB nV-sec kHz nV-sec
Test Conditions/Comments To 0.01%, 10 V voltage swing To 0.01%, 2.5 V voltage swing, AVDD = 5 V 10% to 90%, 10 V voltage swing 10% to 90%, 2.5 V voltage swing
3 dB, VREFP = 5 V +10 Vp-p, VREFN = -10 V. Code transition = 0x7FF to 0x800 and vice versa
Guaranteed by design and characterization, not production tested.
Rev. 0 | Page 5 of 20
AD5726
TIMING CHARACTERISTICS
AVDD = +15 V/+5 V, AVSS = -15 V/-5 V/0 V, GND = 0 V; VREFP = +10 V/+2.5 V; VREFN = -10 V/-2.5 V/0 V, VL = 5 V, RLOAD = 2 k, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. 1, 2 Table 5.
Parameter tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 tLDW tCLRW
1 2
Limit at TMIN, TMAX 5 5 13 13 13 13 20 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns
Description Data setup time. Data hold time. Clock pulse width high. Clock pulse width low. Select time. Deselect delay. Load disable time. Load delay. Load pulse width. Clear pulse width.
Guaranteed by design and characterization, not production tested. All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
tCSH
CS
tCSS
SDIN A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0
SCLK
LDAC
Figure 2. Data Load Sequence
tDS
SDIN
tDH
SCLK
tCL
CS
tCH tCSH
CLRSEL
tLD2
LDAC
tLDW
CLR
tCLRW
tS
06469-003
tS
1LSB
06469-004
VOUT
1LSB
VOUT
Figure 3. Data Load Timing
Figure 4. Clear Timing
Rev. 0 | Page 6 of 20
06469-002
tLD1
tLD2
AD5726 ABSOLUTE MAXIMUM RATINGS
TA = 25C unless otherwise noted. Transient currents up to 100 mA do not cause SCR latch-up. Table 6.
Parameter AVSS to GND AVDD to GND AVSS to AVDD AVSS to VREFN Current into Any Pin Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Lead Temperature Soldering Rating +0.3 V to -17 V -0.3 V to +17 V -0.3 V to +34 V -0.3 V to +AVSS - 2 V 15 mA -0.3 V to +7 V -0.3 V to +7 V -40C to +85C -65C to +150C 105C JEDEC industry standard J-STD-020
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance
Package Type 16-Lead SSOP 16-Lead SOIC JA 151 124.9 JC 28 42.9 Unit C/W C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 7 of 20
AD5726 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD 1 VOUTD 2 VOUTC 3 VREFN 4 VREFP 5 VOUTB 6 VOUTA 7 AVSS 8 NC = NO CONNECT
16 CLRSEL 15 CLR 14 LDAC
AD5726
TOP VIEW (Not to Scale)
13 NC 12 CS 11 SCLK 10 SDIN
06469-005
9
GND
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic AVDD VOUTD VOUTC VREFN VREFP VOUTB VOUTA AVSS GND SDIN SCLK CS NC LDAC Description Positive Analog Supply Pin. Voltage ranges from 5 V to 15 V Buffered Analog Output Voltage of DAC D. Buffered Analog Output Voltage of DAC C. Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output. Allowable range is AVSS to VREFP - 2.5 V. Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage. Allowable range is AVDD - 2.5 V to VREFN + 2.5 V. Buffered Analog Output Voltage of DAC B. Buffered Analog Output Voltage of DAC A. Negative Analog Supply Pin. Voltage ranges from 0 V to -15 V. Ground Reference Pin. Serial Data Input. Data must be valid on the rising edge of SCLK. This input is ignored when CS is high. Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK. Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin is logically OR'ed with the SCLK input and disables the serial data input when high. No Internal Connection. Active Low, Asynchronous Load DAC Input. The data currently contained in the serial input register is transferred out to the DAC data registers on the falling edge of LDAC, independent of CS. Input data must remain stable while LDAC is low. Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or midscale (0x800), depending on the state of CLRSEL. The data in the serial input register is unaffected by this control. Determines the action of CLR. If high, a clear command sets the internal DAC registers to midscale (0x800). If low, the registers are set to zero (0x000).
15 16
CLR CLRSEL
Rev. 0 | Page 8 of 20
AD5726 TYPICAL PERFORMANCE CHARACTERISTICS
0.4 0.3 0.2
INL ERROR (LSB)
0.05
MAX DNL ERROR (LSB)
+85C +25C -40C
0
0.1 0 -0.1 -0.2 -0.3 -0.4 AVDD = +15V AVSS = -15V VREFP = +10V VREFN = -10V 0 500 1000 1500 2000 2500 3000 3500 4000
06469-006
-0.05
-0.10
-0.15 AVDD = 5V AVSS = 0V VREFN = 0V TA = 25C
06469-009
-0.20
-0.25 1.0
1.2
1.4
1.6
1.8
2.0 VREFP (V)
2.2
2.4
2.6
2.8
3.0
DAC (Code)
Figure 6. INL Error vs. DAC Code, VSUPPLY = 15 V, VREFP/VREFN = 10 V
0.20 0.15 0.10
MAX INL ERROR (LSB)
Figure 9. DNL Error vs. VREFP, VSUPPLY = +5 V, VREFN = 0 V
1.0 AVDD = +15V AVSS = -15V VREFN = -10V TA = 25C
+85C +25C -40C
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
DNL ERROR (LSB)
0.05 0 -0.05 -0.10 -0.15 -0.20 AVDD = +15V AVSS = -15V VREFP = +10V VREFN = -10V 0 500 1000 1500 2000 2500 3000 3500 4000
06469-007
-1.0
DAC (Code)
VREFP (V)
Figure 7. DNL Error vs. DAC Code, VSUPPLY = 15 V, VREFP/VREFN = 10 V
1.0 0.8 0.6
MAX DNL ERROR (LSB)
Figure 10. INL Error vs. VREFP, VSUPPLY = 15 V, VREFN = -10 V
0.5 0.4 0.3 AVDD = 5V AVSS = 0V VREFN = 0V TA = 25C
AVDD = +15V AVSS = -15V VREFN = -10V TA = 25C
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
06469-008
MAX INL ERROR (LSB)
0.2 0.1 0 -0.1 -0.2 -0.3
VREFP (V)
VREFP (V)
Figure 8. DNL Error vs. VREFP, VSUPPLY = 15 V, VREFN = -10 V
Figure 11. INL Error vs. VREFP, VSUPPLY = +5 V, VREFN = 0 V
Rev. 0 | Page 9 of 20
06469-011
6
7
8
9
10
11
12
-0.4 1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
06469-010
6
7
8
9
10
11
12
AD5726
0 -0.1
FULL-SCALE ERROR (LSB)
AVDD = +15V AVSS = -15V VREFP = +10V VREFN = -10V 2k LOAD
INL ERROR (LSB)
0.3 0.2 0.1 DAC A DAC B DAC C DAC D
-0.2 -0.3 -0.4 -0.5 DAC B -0.6 -0.7 -40 DAC A
06469-012
DAC D
0 -0.1 -0.2
DAC C
-0.3 -0.4
AVDD = 5V AVSS = 0V VREFP = 2.5V VREFN = 0V TA = 25C 0 500 1000 1500 2000 2500 3000 3500 4000
06469-015
-20
0
20
40
60
80
TEMPERATURE (C)
DAC (Code)
Figure 12. Full-Scale Error vs. Temperature
0.3
Figure 15. Channel-to-Channel Matching, VSUPPLY = +5 V, VREFP = 2.5 V, VREFN = 0 V
16 14 12 10
AIDD (mA)
0.2
ZERO-SCALE ERROR (LSB)
AVDD = +15V AVSS = -15V VREFP = +10V VREFN = -10V 2k LOAD
0.1
0 DAC A -0.1 DAC D DAC C -0.2 DAC B -20 0 20 40 60 80
06469-013
8 6 4 AVDD = +15V AVSS = -15V VREFN = -10V 2 DIGITAL INPUTS HIGH TA = 25C 0 -7 -5 -3 -1 1
TEMPERATURE (C)
VREFP (V)
Figure 13. Zero-Scale Error vs. Temperature
0.3
Figure 16. AIDD vs. VREFP, All DACs Loaded with Full-Scale Code
1.7995 1.5995
AVDD = +15V AVSS = -15V
VREFP = +10V
VREFN = -10V
TA = 25C
0.2
INL ERROR (LSB)
0.1
DAC A DAC B DAC C DAC D
IVREFP (mA)
1.3995 1.1995 0.9995 0.7995 0.5995
0
-0.1 AVDD = +15V AVSS = -15V VREFP = +10V VREFN = -10V TA = 25C
06469-014
0.3995 0.1995
06469-017
-0.2
-0.3
0
500
1000
1500
2000
2500
3000
3500
4000
-0.0005
0
500
1000
1500
2000
2500
3000
3500
4000
DAC (Code)
DAC (Code)
Figure 14. Channel-to-Channel Matching, VSUPPLY = 15 V, VREFP/VREFN = 10 V
Figure 17. IVREFP vs. DAC Code
Rev. 0 | Page 10 of 20
06469-016
-0.3 -40
3
5
7
9
11
13
AD5726
2 0 -2
25 20 15 AVDD = 15V AVSS = 0V VREFP = 10V VREFN = 0V TA = 25C DATA = 0x800
-4
GAIN (dB)
-6 -8 -10 AVDD = +15V -12 AVSS = -15V VREFP = 0V 100mV VREFN = -10V -14 FULL-SCALE CODE LOADED TA = 25C -16 10 100 1k 10k
IOUT (A)
10 5 0 -5 -10
FREQUENCY (Hz)
VOUT (V)
Figure 18. Small Signal Response, VSUPPLY = 15 V, VREFN = -10 V
8 6 IDD
Figure 20. Output Current vs. Output Voltage, VSUPPLY = 15 V, VREFP/VREFN = 10 V
12
POWER SUPPLY CURRENT (mA)
10
4 2 0 -2 -4 -6
FULL-SCALE VOLTAGE (V)
AVDD = +15V AVSS = -15V
AVDD = +15V AVSS = -15V VREFP = +10V VREFN = -10V TA = 25C
8
6
4
ISS
2
06469-019
-15
5
25
45
65
85
0.1
1 LOAD RESISTANCE (k)
10
100
TEMPERATURE (C)
Figure 19. Power Supply Currents vs. Temperature, VSUPPLY = 15 V, VREFP/VREFN = 10 V
Figure 21. Output Swing vs. Load Resistance, VSUPPLY = 15 V, VREFP/VREFN = 10 V
Rev. 0 | Page 11 of 20
06469-021
-8 -35
0 0.01
06469-020
100k
1M
10M
06469-018
0
1
2
3
4
5
6
7
8
9
10
AD5726 TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 7. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5726 is monotonic over its full operating temperature range Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be VREFP - 1 LSB. Full-scale error is expressed in LSBs. A plot of full-scale error vs. temperature can be seen in Figure 12. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) is loaded to the DAC register. Ideally, the output voltage should be VREFN. A plot of zero-scale error vs. temperature can be seen in Figure 13. Zero-Scale Error TC This is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/C. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltageoutput DAC converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/s. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. Analog Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in dB.
Rev. 0 | Page 12 of 20
AD5726 THEORY OF OPERATION
The AD5726 is a quad, 12-bit, serial input, unipolar/bipolar voltage output DAC. It operates from single-supply voltages of +5 V to +15 V or dual supply voltages of 5 V to 15 V. The four outputs are buffered and capable of driving a 2 k load. Data is written to the AD5726 in a 16-bit word format via a 3-wire serial interface. symmetric bipolar waveforms, which require an accurate, low drift bipolar reference. The AD588 provides both voltages and needs no external components. Additionally, the part is trimmed in production for 12-bit accuracy over the full temperature range without user calibration.
AVDD 2.5V MIN VVREFP 0xFFF
DAC ARCHITECTURE
Each of the four DACs is a voltage switched, high impedance (50 k), R-2R ladder configuration. Each 2R resistor is driven by a pair of switches that connect the resistor to either VREFP or VREFN.
OUTPUT AMPLIFIERS
The AD5726 features buffered analog voltage outputs capable of sourcing and sinking up to 5 mA when operating from 15 V supplies, eliminating the need for external buffer amplifiers in most applications while maintaining specified accuracy over the rated operating conditions. The output amplifiers are shortcircuit protected. The designer should verify that the output load meets the capabilities of the device, in terms of both output current and load capacitance. The AD5726 is stable with capacitive loads up to 2 nF typically. However, any capacitance load increases the settling time and should be minimized if speed is a concern. The output stage includes a P-channel MOSFET to pull the output voltage down to the negative supply. This is very important in single-supply systems where VREFN usually has the same potential as the negative supply. With no load, the zeroscale output voltage in these applications are less than 500 V typically, or less than 1 LSB when VREFP = 2.5 V. However, when sinking current, this voltage does increase because of the finite impedance of the output stage. The effective value of the pulldown resistor in the output stage is typically 320 . With a 100 k resistor connected to 5 V, the resulting zero-scale output voltage is 16 mV. Thus, the best single-supply operation is obtained with the output load connected to ground, so the output stage does not have to sink current. Like all amplifiers, the AD5726 output buffers do generate voltage noise, 5 nV/rtHz typically. This is easily reduced by adding a simple RC low-pass filter on each output.
2.5V MIN 1 LSB
0x000 VVREFN 0V MIN AVSS -10V MIN
Figure 22. Output Voltage Range Programming
When driving the reference input, it is important to note that VREFP both sinks and sources current, and that the input currents of both are code dependent. Many voltage reference products have limited current sinking capabilities and must be buffered with an amplifier to drive VREFP to maintain overall system accuracy. The input VREFN, however, has no such requirement. For a single 5 V supply, VREFP is limited to 2.5 V at the most, and must always be at least 2.5 V less than the positive supply to ensure linearity of the device. For these applications, the AD780 is an excellent low drift 2.5 V reference. It works well with the AD5726 in a single 5 V system, as shown in Figure 26. It is recommended that the reference inputs be bypassed with 0.2 F capacitors when operating with 10 V references. This limits the reference bandwidth.
VREFP Input Requirements
The AD5726 uses a DAC switch driver circuit that compensates for different supply, reference voltage, and digital code inputs. This ensures that all DAC ladder switches are always biased equally, ensuring excellent linearity under all conditions. Thus, as indicated in the specifications, the VREFP input of the AD5726 requires both sourcing and sinking current capability from the reference voltage source. Many positive voltage references are intended as current sources only and offer little sinking capability. The user should consider references such as the AD584, AD586, AD587, AD588, AD780, and REF43 for such an application.
REFERENCE INPUTS
The two reference inputs of the AD5726 allow a great deal of flexibility in circuit design. The user must take care, however, to observe the minimum voltage input levels on VREFP and VREFN to maintain the accuracy shown in the data sheet. These input voltages can be set anywhere across a wide range within the supplies, but must be a minimum of 2.5 V apart in any case (see Figure 22). A wide output voltage range can be obtained with 5 V references that can be provided by the AD588 as shown in Figure 24. Many applications utilize the DACs to synthesize
Rev. 0 | Page 13 of 20
06469-022
AD5726
SERIAL INTERFACE
The AD5726 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPITM, MICROWIRETM, and DSP standards.
LOAD DAC (LDAC)
When asserted, the LDAC pin is an asynchronous, active low, digital input that transfers the contents of the input register to the internal data bus, updating the addressed DAC output. New data must not be programmed to the AD5726 while the LDAC pin is low.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the device MSB first as a 16-bit word under the control of a serial clock input SCLK. The input register consists of two address bits, two don't care bits, and 12 data bits as shown in Table 11. The timing diagram for this operation is shown in Figure 2. When CS is low, the data presented to the input SDIN is shifted MSB first into the internal shift register on the rising edge of SCLK. Once all 16 bits of the serial data-word have been input, the load control LDAC is strobed, and the word is latched onto the internal data bus. The two address bits are decoded and used to route the 12-bit data-word to the appropriate DAC data register.
CLR and CLRSEL
The CLR control allows the user to perform an asynchronous clear function. Asserting CLR loads all four DAC registers, forcing the DAC outputs to either zero-scale (0x000) or midscale (0x800), depending on the state of CLRSEL as shown in Table 9. The CLR function is asynchronous and independent of CS. When CLR returns high, the DAC outputs remain at the clear value until LDAC is strobed, reloading the individual DAC registers with either the data held in the input register prior to the clear or with new data loaded through the serial interface. Table 9. CLR/CLRSEL Truth Table
CLR 0 0 1 1 CLRSEL 0 1 0 1 DAC Registers Zero-Scale (0x000) Midscale (0x800) No Change No Change
Operation of CS and SCLK
The CS and SCLK pins are internally fed to the same logical OR gate and, therefore, require careful attention during a load cycle to avoid clocking in false data bits. As shown in the timing diagram in Figure 2, SCLK must be halted high, or CS must be brought high, during the last high portion of SCLK following the rising edge that clocked in the last data bit. Otherwise, an additional rising edge is generated by CS rising while SCLK is low, causing CS to act as the clock and allowing a false data bit into the input shift register. The same must also be considered for the beginning of the data load sequence.
Table 10. DAC Address Word Decode Table
A1 0 0 1 1 A0 0 1 0 1 DAC Addressed DAC A DAC B DAC C DAC D
Coding
The AD5726 uses binary coding. The output voltage can be calculated from the following equation:
VOUT = VREFN +
(VREFP - VREFN )x D
4096
where D is the digital code in decimal. Table 11. Input Register Format
DB0 A1 DB1 A0 DB2 X DB3 X DB4 D11 DB5 D10 DB6 D9 DB7 D8 DB8 D7 DB9 D6 DB10 D5 DB11 D4 DB12 D3 DB13 D2 DB14 D1 DB15 D0
Rev. 0 | Page 14 of 20
AD5726 APPLICATIONS
POWER-UP SEQUENCE
To prevent CMOS latch-up conditions, powering AVDD, AVSS, and GND prior to any reference voltages is recommended. The ideal power-up sequence is GND, AVSS, AVDD, VREFP, VREFN, and the digital inputs. Noncompliance with the power-up sequence over an extended period can elevate the reference currents and eventually damage the device. On the other hand, if the noncompliant power-up sequence condition is as short as a few milliseconds, the device can resume normal operation without damage once AVDD/AVSS are powered up. Figure 24 (symmetrical bipolar operation) shows the AD5726 configured for 10 V operation. See the AD688 datasheet for a full explanation of the reference operation. Adjustments may not be necessary for many applications because the AD688 is a very high accuracy reference. However, if additional adjustments are required, adjust the AD5726 fullscale first. Begin by loading the digital full-scale code (0xFFF). Then, modify the gain adjust potentiometer to attain a DAC output voltage of 9.9976 V. Next, alter the balance adjust to set the midscale output voltage to 0.000 V. The 0.2 F bypass capacitors shown at their reference inputs in Figure 24 should be used whenever 10 V references are used. Applications with single references or references to 5 V may not require the 0.2 F bypassing. The 6.2 resistor in series with the output of the reference amplifier keeps the amplifier from oscillating with the capacitive load. This has been found to be large enough to stabilize this circuit. Larger resistor values are acceptable if the drop across the resistor does not exceed a VBE. Assuming a minimum VBE of 0.6 V and a maximum current of 2.75 mA, the resistor should be under 200 for the loading of a single AD5726. Using two separate references is not recommended. Having two references may cause different drifts with time and temperature, whereas with a single reference, most drifts track. Unipolar positive full-scale operation can usually be set by a reference with the correct output voltage. This is preferable to using a reference and dividing down to the required value. For a 10 V full-scale output, the circuit can be configured as shown in Figure 25. In this configuration, the full-scale value is first set by adjusting the 10 k resistor for a full-scale output of 9.9976 V.
+15V
+15V
6 4 3
REFERENCE CONFIGURATION
Output voltage ranges can be configured as either unipolar or bipolar, and within these choices, a wide variety of options exists. The unipolar configuration can be either a positive (as shown in Figure 23) or a negative voltage output. The bipolar configuration can be either symmetrical (as shown in Figure 24) or nonsymmetrical.
+15V +15V + INPUT OUTPUT
OP1177
VREFP 0.2F
AVDD
ADR01
TRIM 10k VREFN +10V OPERATION
AD5726
0.1F10F
AVSS
06469-023
-15V
Figure 23. Unipolar +10 V Operation
+15V 39k
U1 +15V VIN VOUT
AVDD
6.2 0.2F AVDD VREFP
ADR01
TEMP TRIM +15V U2
VREFP
BALANCE 100k
12
1
AD688 FOR 10V AD588 FOR 5V
5
AD5726
14 15
0.1F10F
0.1F10F
AD5726
VREFN AVSS 0.2F
GND
GAIN 100k
V+
6.2 0.2F
OP1177
V-
06469-025
VREFN AVSS
8
13
7
1F -15V 5 OR 10V OPERATION
06469-024
-15V
0V TO -10V OPERATION
-15V
Figure 25. Unipolar -10 V Operation
Figure 24. Symmetrical Bipolar Operation
Figure 25 shows the AD5726 configured for -10 V to 0 V operation. An ADR01 and OP1177 are configured to produce a -10 V output that is connected directly to VREFP for the reference voltage.
Rev. 0 | Page 15 of 20
AD5726
Single +5 V Supply Operation
For operation with a 5 V supply, the reference voltage should be set between 1.0 V and 2.5 V for optimum linearity. Figure 26 shows an AD780 used to supply a 2.5 V reference voltage. The headroom of the reference and DAC are both sufficient to support a 5 V supply with 5 V tolerance. AVDD and VL should be connected to the same supply. Separate bypassing to each pin should be used.
5V
The ground path (circuit board trace) should be as wide as possible to reduce any effects of parasitic inductance and ohmic drops. A ground plane is recommended if possible. The noise immunity of the on-board digital circuitry, typically in the hundreds of millivolts, is well able to reject the common-mode noise typically seen between system analog and digital grounds. Finally, the analog and digital ground should be connected to each other at a single point in the system to provide a common reference. This is preferably done at the power supply Good grounding practice is essential to maintain analog performance in the surrounding analog support circuitry as well. With two reference inputs and four analog outputs capable of moderate bandwidth and output current, there is a significant potential for ground loops. Again, a ground plane is recommended as the most effective solution to minimize errors due to noise and ground offsets. The AD5726 should have ample supply bypassing located as close to the package as possible. Recommended capacitor values are 10 F in parallel with 0.1 F. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
10F INPUT OUTPUT
0.01F
VREFP 0.2F
AVDD
AD780
TRIM GND 10k
AD5726
VREFN AVSS
0.1F10F
0V TO 2.5V OPERATION SINGLE 5V SUPPLY
Figure 26. 5 V Single-Supply Operation
POWER SUPPLY BYPASSING AND GROUNDING
In any circuit where accuracy is important, careful consideration to the power supply and ground return layout helps to ensure the rated performance. The AD5726 has a single ground pin that is internally connected to the digital section as the logic reference level. The user's first instinct may be to connect this pin to the digital ground; however, in large systems, the digital ground is often noisy because of the switching currents of other digital circuitry. Any noise introduced at the ground pin could couple into the analog output. Thus, to avoid error-causing digital noise in the sensitive analog circuitry, the ground pin should be connected to the system analog ground.
06469-026
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5726 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 27 shows a 4-channel isolated interface connected to the AD5726 using an ADuM1400.
MICROCONTROLLER SERIAL CLOCK OUT SERIAL DATA OUT SYNC OUT CONTROL OUT VIA VIB VIC VID
ADuM1400*
ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE VOA VOB VOC VOD TO SCLK TO SDIN TO CS TO LDAC
06469-027
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 27. Isolated Interface
Rev. 0 | Page 16 of 20
AD5726
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5726 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire interface (minimum) consisting of a clock signal, a data signal, and a synchronization signal. The AD5726 requires a 16-bit data-word with data valid on the falling edge of SCLK. For all the interfaces, the DAC output update can be done automatically when all the data is clocked in, or it can be done under the control of LDAC. The 8xC51 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Because the DAC expects a 16-bit word, CS (P3.3) must be left low after the first eight bits are transferred. After the second byte has been transferred, the P3.3 line is taken high. The DAC can be updated using LDAC via P3.4 of the 8xC51
8xC51*
RxD TxD P3.3 P3.4
AD5726*
SDIN SCLK CS
06469-029
06469-031
MC68HC11 Interface
Figure 28 shows an example of a serial interface between the AD5726 and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1); clock polarity bit (CPOL = 0), and the clock phase bit (CPHA = 1). The SPI is configured by writing to the SPI control register (SPCR); see the 68HC11 User Manual. SCK of the MC68HC11 drives the SCLK of the AD5726, the MOSI output drives the serial data line (SDIN) of the AD5726. The CS is driven from one of the port lines, in this case PC7. When data is being transmitted to the AD5726, the CS line (PC7) is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight falling clock edges occur in the transmit cycle; thus, to load the required 16-bit word, PC7 is not brought high until the second 8-bit word has been transferred to the DACs input shift register.
MC68HC11*
MOSI SCK PC7
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. 8xC51 to AD5726 Interface
PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to pulse CS and enable the serial port of the AD5726. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are needed. Figure 30 shows the connection diagram.
PIC16C6x/7x*
SDO/RC5 SCLK/RC3 RA1
AD5726*
SDIN SCLK CS
06469-030
AD5726*
SDIN SCLK CS
06469-028
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. PIC16C6x/7x to AD5726 Interface
Blackfin(R) DSP interface
Figure 31 shows how the AD5726 can be interfaced to the Analog Devices Blackfin DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5726. It also has programmable I/O pins that can be used to set the state of a digital input such as the LDAC pin.
ADSP-BF531
SPISELx SCK MOSI PF10
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 28. MC68HC11 to AD5726 Interface
8xC51 Interface
The AD5726 requires a clock synchronized to the serial data. For this reason, the 8xC51 must be operated in Mode 0. In this mode, serial data is transferred through RxD, and a shift clock is output on TxD. P3.3 and P3.4 are bit-programmable pins on the serial port and are used to drive CS and LDAC, respectively. The 8Cx51 provides the LSB of its SBUF register as the first bit in the data stream. The user must ensure that the data in the SBUF register is arranged correctly because the DAC expects MSB first. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the falling edge. As a result, no glue logic is required between this DAC and the microcontroller interface.
AD5726*
CS SCLK SDIN LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 31. Blackfin DSP to AD5726 Interface
Rev. 0 | Page 17 of 20
AD5726 OUTLINE DIMENSIONS
6.50 6.20 5.90
16
9
5.60 5.30 5.00
1 8
8.20 7.80 7.40
2.00 MAX
1.85 1.75 1.65 0.38 0.22 8 4 0
0.25 0.09
0.05 MIN COPLANARITY 0.10 0.65 BSC
SEATING PLANE
0.95 0.75 0.55
060106-A
COMPLIANT TO JEDEC STANDARDS MO-150-AC
Figure 32. 16-Lead Shrink Small Outline Package [SSOP] (RS-16) Dimensions shown in millimeters
10.50 (0.4134) 10.10 (0.3976)
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model AD5726YRSZ-500RL7 1 AD5726YRSZ-REEL1 AD5726YRWZ-REEL1 AD5726YRWZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead SSOP 16-Lead SSOP 16-Lead SOIC_W 16-Lead SOIC_W
Package Option RS-16 RS-16 RW-16 RW-16
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
032707-B
AD5726 NOTES
Rev. 0 | Page 19 of 20
AD5726 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06469-0-4/07(0)
Rev. 0 | Page 20 of 20

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